A novel co-design approach for soft errors mitigation in embedded systems

Comunicación presentada en the 11th European Conference on Radiation and its Effects on Components and Systems RADECS 2010, Längenfeld, Austria, September 20-24, 2010.A novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques is presented. Two suites of tools are developed to automatically apply the techniques and to facilitate the trade-offs analyses.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Spain Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research project ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098) (Generalitat Valenciana, Spain)

Development of a Tabletop Setup for the Transient Current Technique Using Two-Photon Absorption in Silicon Particle Detectors

The transient current technique (TCT) is widely used in the field of silicon particle detector development. So far, only laser wavelengths with a photon energy larger than or similar to the silicon bandgap (single photon absorption) were used. Recently, measurements using two-photon absorption (TPA) for silicon detector testing have been carried out for the first time. Excess carriers are only created at the focal point of the laser beam and thus resolution in all three spatial directions could be achieved. The resolution perpendicular to the incident laser beam could be increased roughly by a factor of 10. First measurements using this new method were performed at the Singular Laser Facility of Universidad del Pais Vasco (UPV)/Euskal Herriko Unibertzitatea (EHU). Following the initial success of the method, a compact TPA-TCT setup is under development. A first description of the setup and laser system is presented in this articleThis work was supported in part by the Spanish Ministry of Economy and Competitiveness (MINECO) under Grant FPA2013-48387-C6-1-P and in part by the Wolfgang Gentner Programme of the German Federal Ministry of Education and Research under Grant 05E15CH

Guía docente común de las titulaciones de Ingeniero en Electrónica en las universidades andaluzas

El presente documento constituye el resultado del trabajo elaborado de acuerdo con la Convocatoria de Elaboración de Guías Docentes de Titulaciones Andaluzas conforme al Sistema de Créditos Europeos (años 2005/2006) de la Dirección General de Universidades, dependiente de la Secretaría General de Universidades, Investigación y Tecnología de la Consejería de Innovación, Ciencia y Empresa de la Junta de Andalucía

Application-driven co-design of fault-tolerant industrial systems

This paper presents a novel methodology for the HW/SW co-design of fault tolerant embedded systems that pursues the mitigation of radiation-induced upset events (which are a class of Single Event Effects - SEEs) on critical industrial applications. The proposal combines the flexibility and low cost of Software Implemented Hardware Fault Tolerance (SIHFT) techniques with the high reliability of selective hardware replication. The co-design flow is supported by a hardening platform that comprises an automatic software hardening environment and a hardware tool able to emulate Single Event Upsets (SEUs). As a case study, we selected a soft-micro (PicoBlaze) widely used in FPGA-based industrial systems, and a fault tolerant version of the matrix multiplication algorithm was developed. Using the proposed methodology, the design was guided by the requirements of the application, leading us to explore several trade-offs among reliability, performance and cost.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research projects ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098) (Generalitat Valenciana) and ’Aceleración hardware de algoritmos industriales para el sector calzado’ (GRE08-P11) (University of Alicante)

A compiler-based infrastructure for fault-tolerant co-design

The protection of processor-based systems to mitigate the harmful effects of transient faults (hardening) is gaining importance as technology shrinks. Hybrid hardware/software hardening approaches are promising alternatives in the design of such fault tolerant systems. This paper presents a compiler-based infrastructure for facilitating the exploration of the design space between hardware-only and software-only fault tolerant techniques. The compiler design is based on a generic architecture that facilitates the implementation of software-based techniques, providing an uniform isolated-from-target hardening core. In this way, these methods can be implemented in an architecture independent way and can easily integrate new protection mechanisms to automatically produce hardened code. The infrastructure includes a simulator that provides information about memory and execution time overheads to aid the designer in the co-design decisions. The tool-chain is complemented by a hardware fault emulation tool that allows to measure the fault coverage of the different solutions running on the real system. A case study was implemented allowing to evaluate the flexibility of the infrastructure to fit the reliability requirements of the system within their memory and performance restrictions.This work makes part of RENASER project (ESP2007-65914-C03-03) funded by the 2007 Spain Research National Plan of the Ministry of Science and Education in which context this work has been possible. The work presented here has been carried out thanks to the support of the research project 'Aceleracióon de algoritmos industriales y de seguridad en entornos críticos mediante hardware' (GV/2009/098) (Generalitat Valenciana, Spain)

Prototipado rápido de sistemas empotrados tolerantes a radiación en FPGA

La creciente capacidad de integración de las FPGA está convirtiendo estos dispositivos en la plataforma preferida para el prototipado rápido de sistemas digitales complejos. Por otro lado, a medida que la tecnología se reduce, cobra importancia la protección de los sistemas frente a los fallos transitorios inducidos por radiación (por ejemplo los Single Event Upsets). En este trabajo se presenta una nueva aproximación de prototipado rápido para el codiseño de sistemas empotrados robustos usando FPGA. Dicha aproximación está soportada por una plataforma de endurecimiento que permite combinar técnicas de tolerancia a fallos basadas en software con técnicas basadas en hardware, obteniendo diferentes configuraciones hardware/software con diferentes niveles de compromiso entre restricciones de diseño, fiabilidad y coste. Como caso de estudio, se han desarrollado varios sistemas empotrados tolerantes a radiación basados en una versión del microprocesador PicoBlaze independiente de tecnología.Este trabajo ha sido financiado por los siguientes proyectos: 'RENASER' (ESP2007-65914-C03-03) del Plan Nacional de Investigación 2007 del Ministerio de Ciencia y Educación; y el proyecto de investigación 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware' (GV/2009/098) (Generalitat Valenciana, España)

Rapid prototyping of radiation-tolerant embedded systems on FPGA

Technological advances of Field Programmable Gate Array (FPGA) are making that this technology becomes the most preferred platform for the rapid prototyping of highly integrated digital systems. In addition, protection of processor-based systems to mitigate the harmful effects of radiation-induced upset events is gaining importance while technology shrinks. In this context, the main contribution of this work is a novel rapid prototyping approach for the codesign of dependable embedded systems using FPGA. This is supported by a hardening platform that allows combining software-only fault-tolerance techniques with hardware-only approaches, representing several trade-offs among design constraints, reliability and cost. As case study, several radiation-tolerant embedded systems have been developed based on a technology-independent version of the Picoblaze processor.This work was funded by the Ministry of Science and Education in Spain with the RENASER project (ESP2007-65914-C03-03) and the Generalitat Valenciana in Spain with the research project ’Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware’ (GV/2009/098)

Mitigación automática de soft-errors en nuevas aplicaciones de los sistemas empotrados

Las crecientes prestaciones de los microprocesadores, derivadas de la miniaturización de las tecnologías electrónicas, están provocando la aparición de nuevas aplicaciones de los sistemas empotrados en todos los ámbitos. Sin embargo, el empleo de las tecnologías nanométricas conlleva una mayor sensibilidad de los procesadores a los fallos transitorios inducidos por radiación (soft-errors). Por tanto, en el desarrollo de las nuevas generaciones de estos sistemas, y no solo en aquellos que deben trabajar en ambientes de alta radiación, la fiabilidad se está convirtiendo en un factor de creciente importancia. En este trabajo se presenta una infraestructura basada en compilador que permite el co-diseño de estos nuevos sistemas donde la tolerancia a fallos es un parámetro tan relevante como lo pueden ser el coste, el consumo o el rendimiento. Las herramientas desarrolladas facilitan la exploración del espacio de diseño existente entre las técnicas de protección puramente hardware y las técnicas basadas en la redundancia del software. De esta forma se obtienen soluciones híbridas con un mejor balance entre los distintos requisitos del diseño, habilitando a los sistemas empotrados para abordar nuevas aplicaciones de seguridad y misión crítica.Este trabajo ha sido financiado por los siguientes proyectos: 'RENASER' (ESP2007-65914-C03-03) del Ministerio de Ciencia y Educación; y 'Aceleración de algoritmos industriales y de seguridad en entornos críticos mediante hardware' (GV/2009/098) (Generalitat Valenciana)

TCAD Device Simulations of Irradiated Silicon Detectors

The high hadron fluences expected during the HL-LHC programme will damage the silicon detectors. New TCAD simulation models are needed to understand the expected detector behaviour. This review examines the challenges ahead for different kind of detector devices, with attention to the acceptor removal effect in LGADs, surface damage for Monolithics and Strips and bulk damage in all sensor types

Hardening development environment for embedded systems

Artículo y presentación en The 2nd HiPEAC Workshop on Design for Reliability (DFR’10), January 24th, 2010 Pisa, Italy.This paper presents a novel low cost development environment for automatic hardening against Single Event Effects (SEE) of embedded systems through software redundancy. The environment is based on a generic architecture to handle multiple targets and is comprised of an automatic hardening compiler and an instruction set simulator. As a case study, it is developed a compiler back-end for the PicoBlaze soft-micro and implemented several fault tolerance techniques.European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC